Quartus II/ ModelSim을 이용한 구현 - 5. Latch, Flip-Flop
2023. 1. 30. 14:19ㆍ기록지/컴퓨터구조(computer architecture)
5. Latch와 Flip-Flop(set/reset) 구현
원리
D Latch
Clock이 enable 상태를 유지하는 동안 입력 D값의 변화를 출력한다.
D Flip-Flop
Clock의 rising edge나 falling edge에서만 D값으로 출력이 바뀌게 된다. 다른 경우에는
D값이 바뀌더라도 이전 Q값을 그대로 유지한다.
Resettable D Flip-Flop
D flip-flop에 reset 기능이 추가된 D flip-flop이다. Active low에 동작하는 것을 구현 했으며 active low에 동작한다는 말은 reset의 값이 0일 때, reset의 기능을 수행한다는 의미이다.
Set/Resettable D Flip-Flop
D flip-flop에 reset과 set 기능이 추가된 D flip-flop이다. Set과 reset이 Active low에 동작하며 reset신호가 set신호보다 우선순위를 가지고 있다.
설계 검증
D Latch
D Flip-Flop
Enabled D Flip-Flop
Resettable D Flip-Flop
Synchronous Set/Resettable D Flip-Flop
Register
Async/Sync Set/Resettable D Flip-Flop
Nand gate 4개를 이용해서 D latch를 구현
////////////////////////////////////////////////////
//ORGANIZATION : Kwangwoon Univ. Computer Engineering
//NAME : Jinhan Shin(sjh900716@gmail.com)
//PLATFORM : Windows 7
//SIMULATOR : ModelSim-Altera 6.5
//COMPILER : Altera Quartus II 11.0 SP1
//TARGET BOARD : Altera DE2-70
//DESCRIPTION : latch, flip-flop
//LAST UPDATE : Dec. 31, 2013
////////////////////////////////////////////////////
module _dff(clk, d, q, q_bar); // d flip-flop
input clk,d;
output q, q_bar;
wire clk_bar,w_q;
_inv U0_inv (.a(clk),.y(clk_bar)); // Instace of inv
_dlatch U1_dlatch (.clk(clk_bar),.d(d),.q(w_q)); // Instace of dlatch
_dlatch U2_dlatch (.clk(clk),.d(w_q),.q(q),.q_bar(q_bar)); // Instace of dlatch
endmodule
module _dff_en(clk, en, d, q); // enable d flip-flop
input clk, en, d;
output q;
wire w_d;
mx2 U0_mx2 (.y(w_d),.d0(q),.d1(d),.s(en)); // Instance of mx2
_dff U1_dff (.clk(clk),.d(w_d),.q(q)); // Instance of dff
endmodule
module _dff_r(clk, reset_n, d, q); // resettable d flip flop
input clk, reset_n, d;
output q;
wire w_d;
_and2 U0_and2 (.a(d),.b(reset_n),.y(w_d)); // Instance of and2
_dff U1_dff (.clk(clk),.d(w_d),.q(q)); // Instance of dff
endmodule
module _dff_rs(clk, set_n, reset_n, d, q); // resettable/settable d flip flop
input clk, set_n, reset_n, d;
output q;
wire w_d1, w_d2;
_or2 U0_or2 (.a(d),.b(~set_n),.y(w_d1)); // Instance of or2
_and2 U1_and2 (.a(w_d1),.b(reset_n),.y(w_d2)); // Instance of and2
_dff U2_dff (.clk(clk),.d(w_d2),.q(q)); // Instance of dff
endmodule
module _dff_rs_async(clk, set_n, reset_n,d,q); // reset/settable d flip flop asyncronous
input clk, set_n, reset_n, d;
output q;
reg q;
always@(posedge clk or negedge set_n or negedge reset_n) // work when clk rising edge or set_n,reset_n falling edge
begin
if(reset_n==0) q<=1'b0;
else if(set_n==0) q<=1'b1;
else q<=d;
end
endmodule
module _dff_rs_sync(clk, set_n, reset_n,d,q); // reset/settable d flip flop syncronous
input clk, set_n, reset_n, d;
output q;
reg q;
always@(posedge clk) // work when clk rising edge
begin
if(reset_n==0) q<=1'b0;
else if(set_n==0) q<=1'b1;
else q<=d;
end
endmodule
module _dff_rs_sync_async(clk, set_n, reset_n,d,q_sync,q_async); // instance of syncronous and asyncronous
input clk, set_n, reset_n, d;
output q_sync, q_async;
_dff_rs_sync U0_dff_rs_sync(.clk(clk),.set_n(set_n),.reset_n(reset_n),.d(d),.q(q_sync));
_dff_rs_async U1_dff_rs_async(.clk(clk),.set_n(set_n),.reset_n(reset_n),.d(d),.q(q_async));
endmodule
module _dlatch(clk, d, q, q_bar); // dlatch
input clk,d;
output q, q_bar;
wire d_bar, r, s;
_inv U0_inv (.a(d),.y(d_bar)); // Instance of inv
_and2 U1_and2 (.a(clk),.b(d_bar),.y(r)); // Instance of and2
_and2 U2_and2 (.a(clk),.b(d),.y(s)); // Instance of and2
_srlatch U3_srlatch (.r(r),.s(s),.q(q),.q_bar(q_bar)); // Instance of srlatch
endmodule
module _register8(clk,d,q); // 8bit register
input clk;
input [7:0] d;
output [7:0] q;
_dff U0_dff (.clk(clk),.d(d[0]),.q(q[0])); // Instance of dff
_dff U1_dff (.clk(clk),.d(d[1]),.q(q[1])); // Instance of dff
_dff U2_dff (.clk(clk),.d(d[2]),.q(q[2])); // Instance of dff
_dff U3_dff (.clk(clk),.d(d[3]),.q(q[3])); // Instance of dff
_dff U4_dff (.clk(clk),.d(d[4]),.q(q[4])); // Instance of dff
_dff U5_dff (.clk(clk),.d(d[5]),.q(q[5])); // Instance of dff
_dff U6_dff (.clk(clk),.d(d[6]),.q(q[6])); // Instance of dff
_dff U7_dff (.clk(clk),.d(d[7]),.q(q[7])); // Instance of dff
endmodule
module _register32(clk,d,q); // 32bit register
input clk;
input [31:0] d;
output [31:0] q;
_register8 U0_register8 (.clk(clk),.d(d[7:0]),.q(q[7:0])); // Instance of register8
_register8 U1_register8 (.clk(clk),.d(d[15:8]),.q(q[15:8])); // Instance of register8
_register8 U2_register8 (.clk(clk),.d(d[23:16]),.q(q[23:16])); // Instance of register8
_register8 U3_register8 (.clk(clk),.d(d[31:24]),.q(q[31:24])); // Instance of register8
endmodule
module _srlatch(r,s,q,q_bar); // srlatch
input r,s;
output q, q_bar;
_nor2 U0_nor2(.a(r),.b(q_bar),.y(q));
_nor2 U1_nor2(.a(q),.b(s),.y(q_bar));
endmodule
//2-input inverter gate
module _inv(a,y);
input a;
output y;
assign y=~a;
endmodule
//2-input nand2 gate
module _nand2(a,b,y);
input a,b;
output y;
assign y=~(a&b);
endmodule
//2-input and gate
module _and2(a,b,y);
input a,b;
output y;
assign y=a&b;
endmodule
//2-input or gate
module _or2(a,b,y);
input a,b;
output y;
assign y=a|b;
endmodule
//2-input exclusive or gate
module _xor2(a,b,y);
input a,b;
output y;
wire w1,w2,w3,w4;
_inv _inv0(.a(a),.y(w1));
_inv _inv1(.a(b),.y(w2));
_and2 _and0(.a(a),.b(w2),.y(w3));
_and2 _and1(.a(b),.b(w1),.y(w4));
_or2 _or0(.a(w3),.b(w4),.y(y));
endmodule
//3-input and gate
module _and3(a,b,c,y);
input a,b,c;
output y;
assign y=a&b&c;
endmodule
//4-input and gate
module _and4(a,b,c,d,y);
input a,b,c,d;
output y;
assign y=a&b&c&d;
endmodule
//5-input and gate
module _and5(a,b,c,d,e,y);
input a,b,c,d,e;
output y;
assign y=a&b&c&d&e;
endmodule
//3-input or gate
module _or3(a,b,c,y);
input a,b,c;
output y;
assign y=a|b|c;
endmodule
//4-input or gate
module _or4(a,b,c,d,y);
input a,b,c,d;
output y;
assign y=a|b|c|d;
endmodule
//5-input or gate
module _or5(a,b,c,d,e,y);
input a,b,c,d,e;
output y;
assign y=a|b|c|d|e;
endmodule
//4 bits inverter
module _inv_4bits(a,y);
input [3:0] a;
output [3:0] y;
assign y=~a;
endmodule
//4 bits 2-to-1 and gate
module _and2_4bits(a,b,y);
input [3:0] a,b;
output [3:0] y;
assign y=a&b;
endmodule
//4 bits 2-to-1 or gate
module _or2_4bits(a,b,y);
input [3:0] a,b;
output [3:0] y;
assign y=a|b;
endmodule
//4 bits 2-to-1 exclusive or gate
module _xor2_4bits(a,b,y);
input [3:0] a,b;
output [3:0] y;
_xor2 U0_xor2(.a(a[0]), .b(b[0]), .y(y[0]));
_xor2 U1_xor2(.a(a[1]), .b(b[1]), .y(y[1]));
_xor2 U2_xor2(.a(a[2]), .b(b[2]), .y(y[2]));
_xor2 U3_xor2(.a(a[3]), .b(b[3]), .y(y[3]));
endmodule
//4 bits 2-to-1 exclusive nor gate
module _xnor2_4bits(a,b,y);
input [3:0] a,b;
output [3:0] y;
wire [3:0] w0;
_xor2_4bits U0_xor2_4bits(.a(a), .b(b), .y(w0));
_inv_4bits U1_inv_4bits(.a(w0), .y(y));
endmodule
//32 bits inverter
module _inv_32bits(a,y);
input [31:0] a;
output [31:0] y;
assign y=~a;
endmodule
//32 bits 2-to-1 and gate
module _and2_32bits(a,b,y);
input [31:0] a,b;
output [31:0] y;
assign y=a&b;
endmodule
//32 bits 2-to-1 or gate
module _or2_32bits(a,b,y);
input [31:0] a,b;
output [31:0] y;
assign y=a|b;
endmodule
//32 bits exclusive or gate
module _xor2_32bits(a,b,y);
input [31:0] a,b;
output [31:0] y;
_xor2_4bits U0_xor2_4bits(.a(a[3:0]), .b(b[3:0]), .y(y[3:0]));
_xor2_4bits U1_xor2_4bits(.a(a[7:4]), .b(b[7:4]), .y(y[7:4]));
_xor2_4bits U2_xor2_4bits(.a(a[11:8]), .b(b[11:8]), .y(y[11:8]));
_xor2_4bits U3_xor2_4bits(.a(a[15:12]), .b(b[15:12]), .y(y[15:12]));
_xor2_4bits U4_xor2_4bits(.a(a[19:16]), .b(b[19:16]), .y(y[19:16]));
_xor2_4bits U5_xor2_4bits(.a(a[23:20]), .b(b[23:20]), .y(y[23:20]));
_xor2_4bits U6_xor2_4bits(.a(a[27:24]), .b(b[27:24]), .y(y[27:24]));
_xor2_4bits U7_xor2_4bits(.a(a[31:28]), .b(b[31:28]), .y(y[31:28]));
endmodule
//32 bits exclusive nor gate
module _xnor2_32bits(a,b,y);
input [31:0] a,b;
output [31:0] y;
_xnor2_4bits U0_xnor2_4bits(.a(a[3:0]), .b(b[3:0]), .y(y[3:0]));
_xnor2_4bits U1_xnor2_4bits(.a(a[7:4]), .b(b[7:4]), .y(y[7:4]));
_xnor2_4bits U2_xnor2_4bits(.a(a[11:8]), .b(b[11:8]), .y(y[11:8]));
_xnor2_4bits U3_xnor2_4bits(.a(a[15:12]), .b(b[15:12]), .y(y[15:12]));
_xnor2_4bits U4_xnor2_4bits(.a(a[19:16]), .b(b[19:16]), .y(y[19:16]));
_xnor2_4bits U5_xnor2_4bits(.a(a[23:20]), .b(b[23:20]), .y(y[23:20]));
_xnor2_4bits U6_xnor2_4bits(.a(a[27:24]), .b(b[27:24]), .y(y[27:24]));
_xnor2_4bits U7_xnor2_4bits(.a(a[31:28]), .b(b[31:28]), .y(y[31:28]));
endmodule
//2-input nor gate
module _nor2(a,b,y);
input a,b;
output y;
assign y=~(a|b);
endmodule
module mx2 (y, d0, d1, s); // 2-to-1 multiplexer module
input d0, d1, s; // input
output y; // output
wire w0,w1,sb; // wire
iv iv0(.a(s),.y(sb)); // inverter :iv0 a-> s, y-> sd
nd2 nd20(.a(d0),.b(sb),.y(w0)); // nand: nd20 a->d0, b->sb, y->w0
nd2 nd21(.a(d1),.b(s),.y(w1)); // nand: nd21 a->d1, b->s, y->w1
nd2 nd22(.a(w0),.b(w1),.y(y)); // nand: nd22 a->w0, b->w1, y->y
endmodule
module iv(a,y); // inverter module
input a; // input
output y; // output
assign y=~a; // inverter
endmodule
module nd2(a,b,y); // nand module
input a,b; // input
output y; // output
assign y=~(a&b); // nand
endmodule728x90